This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors.
Current radhard-by-design technology for single event errors include triplication (triple mode redundancy, TMR) or duplication (e.g., built-in soft-error resilience, BiSER). These circuits carry two or more redundant copies of a signal, and use some form of voting, or filtering, circuitry to determine the correct signal among the redundant signals. Filtering preventing a signal to pass in the case that one of the redundant signals is wrong (by comparing the value of the redundant signals), and voting circuits selects the correct signal from the majority among several (3 or more) redundant signals. These techniques generate undesirable power and area overhead, and current versions of these techniques cannot handle MBUs or SEMUs. Error correction codes, ECC, for memory, which also (loosely) could be classified as RHBD, is more efficient than duplication/triplication and can, with additional overhead, handle multiple errors in memory circuitry. However, the application of a corresponding error correction to logic circuits is very limited and application specific (e.g., selective parity check or insertion of specialized checking circuit IP).
State-of-the art for layout techniques for soft-error hard design mainly consist of simple spacing and sizing, and in adding additional contacts. The circuit cells and layout methodology in patent (US2009/0184733), on which the new inventions in this application are built, are a new way to protect against soft-errors using layout design techniques.